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FEATURES IDD Total, 7.5 mA Bandwidth RF/IF, 2.4 GHz/1.0 GHz 2.7 V to 3.3 V Power Supply Separate V P Allows Extended Tuning Voltage Programmable Dual Modulus Prescaler RF and IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Analog and Digital Lock Detect Fastlock Mode Power-Down Mode 20-Lead TSSOP and 20-Lead MLF Chip Scale Package APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Cable TV Tuners (CATV) Communications Test Equipment
Dual Low Power PLL Frequency Synthesizer ADF4212L
GENERAL DESCRIPTION
The ADF4212L is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the up-conversion and down-conversion sections of wireless receivers and transmitters. It can provide the LO for both the RF and IF sections. It consists of a low noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual modulus prescaler (P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with external loop filters and VCOs (Voltage Controlled Oscillators). Control of all the on-chip registers is via a simple 3-wire interface with 1.8 V compatibility. The devices operate with a power supply ranging from 2.6 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VP1 VP2 RSET
ADF4212L
12-BIT IF B-COUNTER IFIN IF PRESCALER 6-BIT IF A-COUNTER
IF PHASE FREQUENCY DETECTOR
REFERENCE
CHARGE PUMP IF CURRENT SETTING IF LOCK DETECT IFCP3 IFCP2 IFCP1
CPIF
REFIN
OSCILLATOR 14-BIT IF R-COUNTER
CLOCK DATA LE
22-BIT DATA SDOUT REGISTER 14-BIT RF R-COUNTER RF LOCK DETECT
OUTPUT MUX
MUXOUT
RFCP3 RFCP2 RFCP1 REFERENCE
12-BIT RF B-COUNTER RFIN RF PRESCALER 6-BIT RF A-COUNTER RF PHASE FREQUENCY DETECTOR
CHARGE PUMP
CPRF
REFERENCE RSET FLO SWITCH FLO
DGNDRF
AGNDRF
DGNDIF
AGNDIF
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
1 V 2= ADF4212L-SPECIFICATIONS1 (V dBm= referred2.7 V50to 3.3 V; V 1, V 2 = V AGND = DGND = 0 V; T = T to T , unless otherwise noted; to .)
DD DD P P IF IF A MIN MAX
DD
to 5.5 V; AGNDRF = DGNDRF =
Parameter RF/IF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity IF Input Frequency (IFIN) IF Input Sensitivity MAXIMUM ALLOWABLE Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1 VDD2 VP1, VP2 IDD5 (RF and IF) RF Only IF Only IP (IP1 + IP2) Low Power Sleep Mode
B Version 0.2/2.4 -10/0 100/1000 -10/0 200 10/150 -5 10 100 75
B Chips2 (Typical) 0.2/2.4 -10/0 100/1000 -10/0 200 10/150 -5 10 100 75
Unit GHz min/max dBm min/max MHz min/max dBm min/max MHz max
Test Conditions/Comments For Operation below FMIN, Use a Square Wave VDD = 3 V VDD = 3 V
See Figure 2 for Input Circuit. MHz min/max dBm min pF max A max MHz max Programmable: See Table V. With RSET = 2.7 k With RSET = 2.7 k 0.5 V < VCP < VP - 0.5 2% typ 0.5 V < VCP < VP - 0.5 VCP = VP/2 AC-Coupled. When DC-Coupled, 0 to VDD Max (CMOS-Compatible)
5 625 2 1.5/5.6 1 6 2 2 1.4 0.6 1 10 1.4 0.4 2.7/3.3 VDD1 VDD1/5.5 10 6 4 0.6 1
5 625 2 1.5/5.6 1 6 2 2 1.4 0.6 1 10 1.4 0.4 2.7/3.3 VDD1 VDD1/5.5 10 6 4 0.6 1
mA typ A typ % typ k min/max nA max % typ % typ % typ V min V max A max pF max V min V max V min/V max V min/V max mA max mA max mA max mA typ A typ
Open Drain 1 k Pull-Up to 1.8 V IOL = 500 A
7.5 mA Typical 5.0 mA Typical 2.5 mA Typical
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 Guaranteed by design. Sample tested to ensure compliance. 5 TA = 25C. RF = 1 GHz. Prescaler = 32/33. IF = 500 MHz. Prescaler = 16/17.
Specifications subject to change without notice.
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ADF4212L
2= to 5.5 V ; AGND SPECIFICATIONS1 T(V =1T= Vto2T= 2.7 V to 3.3 V; V 1, Vnoted;VdBm referred to 50 = DGND , unless otherwise .)
DD DD P P DD RF A MIN MAX RF
= AGNDIF = DGNDIF = 0 V;
Parameter NOISE CHARACTERISTICS RF Phase Noise Floor3 Phase Noise Performance4 IF: 540 MHz Output5 IF: 900 MHz Output6 RF: 900 MHz Output6 RF: 1750 MHz Output7 RF: 2400 MHz Output8 Spurious Signals IF: 540 MHz Output5 IF: 900 MHz Output6 RF: 900 MHz Output6 RF: 1750 MHz Output7 RF: 2400 MHz Output8
B Version -170 -162 -89 -87 -89 -84 -87 -88/-90 -90/-94 -90/-94 -80/-82 -80/-82
B Chips2 -170 -162 -89 -87 -89 -84 -87 -88/-90 -90/-94 -90/-94 -80/-82 -80/-82
Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dB typ dB typ dB typ dB typ dB typ
Test Conditions/Comments @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency See Note 9 See Note 9 See Note 9 @ 1 kHz Offset and 1 MHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency See Note 9 See Note 9 See Note 9 @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C 2 The B Chip specifications are given as typical values. 3 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). See TPC 14. 4 The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer. (f REFOUT = 10 MHz @ 0 dBm) 5 fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f IF = 540 MHz; N = 2700; Loop B/W = 20 kHz 6 fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz 7 fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 1750 MHz; N = 8750; Loop B/W = 20 kHz 8 fREFIN = 10 MHz; f PFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 2400 MHz; N = 9800; Loop B/W = 20 kHz 9 Same conditions as listed on the preceding line. Specifications subject to change without notice.
TIMING CHARACTERISTICS T = T
Parameter t1 t2 t3 t4 t5 t6 Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; .) A MIN to TMAX, unless otherwise noted; dBm referred to 50
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Set-Up Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Set-Up Time LE Pulsewidth
Guaranteed by design but not production tested. Specifications subject to change without notice.
t3
CLOCK
t4
t1
DATA DB20 (MSB)
t2
DB19 DB2 DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
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ADF4212L
ABSOLUTE MAXIMUM RATINGS 1, 2, 3
(TA = 25C, unless otherwise noted.)
VDD1 to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V VP1, VP2 to VDD1, VDD2 . . . . . . . . . . . . . . . -0.3 V to +3.6 V Digital I/O Voltage to GND . . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V REFIN, RFIN, IFIN to GND . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W CSP JA Thermal Impedance (Paddle Soldered) . . . 122C/W CSP JA Thermal Impedance (Paddle Not Soldered) 216C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V
ORDERING GUIDE
Model ADF4212LBRU ADF4212LBCP
Temperature Range -40C to +85C -40C to +85C
Package Option* RU-20 CP-20
*RU = Thin Shrink Small Outline Package (TSSOP) CP = Chip Scale Package Contact the factory for chip availability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4212L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TSSOP
1 2 3 4 5 6 7 8 9 10 20 19 18 17
LFCSP
VDD1
VP2 CPIF DGNDIF IFIN AGNDIF RSET LE DATA CLK
VP1 CPRF DGNDRF RFIN AGNDRF FLO REFIN DGNDIF MUXOUT
CPRF DGNDRF RFIN AGNDRF FLO
VP1
VDD1
VDD2
1 2 3 4 5
20 19 18 17 16
VDD2 VP2 CPIF
15 14 13
DGNDIF IFIN AGNDIF RSET LE
ADF4212L
CHIP SCALE PACKAGE
6 7 8 9 10
ADF4212L
TOP VIEW (Not To Scale)
16 15 14 13 12 11
12 11
REFIN
-4-
MUXOUT CLK DATA
DGNDIF
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ADF4212L
PIN FUNCTION DESCRIPTION
Mnemonic CPRF DGNDRF RFIN AGNDRF FLO REFIN DGNDIF MUXOUT CLK DATA LE RSET
Description RF Charge Pump Output. When enabled, this provides ICP to the external RF loop filter, which in turn drives the external RF VCO. Digital Ground Pin for the RF Digital Circuitry Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO. Ground Pin for the RF Analog Circuitry Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground Pin for the IF Digital, Interface, and Control Circuitry This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF, or the scaled Reference Frequency to be accessed externally. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I CP MAX = 13.5 RSET
AGNDIF IFIN CPIF V P2 VDD2 VDD1 V P1
so, with RSET = 2.7 k, ICP MAX = 5 mA for both the RF and IF Charge Pumps. Ground Pin for the IF Analog Circuitry Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO. Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where VDD2 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V. Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the same potential as VDD1. Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where VDD1 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.
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ADF4212L-Typical Performance Characteristics
0 0 -10 -5 VDD = 3 V VP = 5 V -20 REFERENCE LEVEL = -3.0dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1Hz VIDEO BANDWIDTH = 1Hz SWEEP = 2.5 SECONDS AVERAGES = 20
OUTPUT POWER - dB
AMPLITUDE - dBm
-10
-30 -40 -50 -60 -70
-15
-20
-85.9dB -80 -25 -90 -30 0 500 1000 1500 2000 2500 3000 FREQUENCY - MHz -100 -400k -200k 1.75G FREQUENCY - Hz 200k 400k
TPC 1. Input Sensitivity (RF Input)
TPC 4. Reference Spurs, RF Side (1750 MHz, 200 kHz, 20 kHz)
10dB/DIV
0 -5 -10
VDD = 3 V VP = 5 V
RL = -50dBc/Hz
rms NOISE = 1.38 DEGREES 1.38" rms
-50 -60 -70
PHASE NOISE - dBc/Hz
500 1000 1500
AMPLITUDE - dBm
-80 -90 -100 -110 -120 -130
-15
-20 -25 -30
-140
-35 0 FREQUENCY - MHz
-150 100Hz FREQUENCY OFFSET FROM 1.75GHz CARRIER
1MHz
TPC 2. Input Sensitivity (IF Input)
TPC 5. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)
0 -10 -20
OUTPUT POWER - dB
0
OUTPUT POWER - dB
-30 -40 -50 -60 -70 -80
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 22
REFERENCE LEVEL = -3.2dBm
-10 -20 -30 -40 -50 -60 -70 -80
REFERENCE LEVEL = -4.3dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 22
-84.2dBc/Hz -90 -100 -2k -1k 1.75G FREQUENCY - Hz 1k 2k
-90 -100 -2k -1k 540M FREQUENCY - Hz
-88.8dBc/Hz 1k 2k
TPC 3. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)
TPC 6. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)
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ADF4212L
0 -10 -20 REFERENCE LEVEL = -7.0dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1Hz VIDEO BANDWIDTH = 1Hz SWEEP = 2.5 SECONDS AVERAGES = 20
-130 VDD = 3V VP = 5V -140
PHASE NOISE - dBc/Hz
OUTPUT POWER - dB
-30 -40 -50 -60 -70
-150
-160
-89.3dBc -80 -90 -100 -400k -200k 200k 540M FREQUENCY - Hz 400k
-170
-180 10 100 1000 PHASE DETECTOR FREQUENCY - kHz 10000
TPC 7. Reference Spurs, IF Side (540 MHz, 200 kHz, 20 kHz)
TPC 10. Phase Noise Referred to CP Output vs. PFD Frequency, IF Side
10dB/DIV -50
RL = -50dBc/Hz
rms NOISE = 0.83 DEGREES
6
0.83" rms
-60 -70
4
PHASE NOISE - dBc/Hz
-80
2
ICP - mA
-90 -100 -110
0
-2
-120 -130 -140 -150 100Hz FREQUENCY OFFSET FROM 540MHz CARRIER
-4
-6
1MHz
0
1
2 VCP - V
3
4
5
TPC 8. Integrated Phase Noise (540 MHz, 200 kHz/20 kHz)
TPC 11. RF Charge Pump Output Characteristics
6
-130 VDD = 3V VP = 5V -140
PHASE NOISE - dBc/Hz
4 VDD = 3V VP2 = 5.5V 2
ICP - mA
-150
0
-160
-2
-170
-4
-180 10 100 1000 PHASE DETECTOR FREQUENCY - kHz 10000
-6 0 1 2 VCP - V 3 4 5
TPC 9. Phase Noise Referred to CP Output vs. PFD Frequency, RF Side
TPC 12. IF Charge Pump Output Characteristics
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ADF4212L
0
0 -10
FIRST REFERENCE SPUR - dBc/Hz
-20
-20
PHASE NOISE - dBc/Hz
0 1 2 3 4 5
-30 -40 -50 -60 -70 -80 -90
-40
-60
-80
-100 TUNING VOLTAGE - V
-100 -40
-20
0
20
40
60
80
100
TEMPERATURE - C
TPC 13. RF Reference Spurs (200 kHz) vs. VTUNE (1750 MHz, 200 kHz, 20 kHz)
0
TPC 16. IF Phase Noise vs. Temperature (540 MHz, 200 kHz, 20 kHz)
0 -10
FIRST REFERENCE SPUR - dBc
-20
-20
PHASE NOISE - dBc/Hz
0 1 2 3 4 5
-40
-30 -40 -50 -60 -70 -80 -90
-60
-80
-100
-120 TUNING VOLTAGE - V
-100 0 1 2 3 4 5 TUNING VOLTAGE - V
TPC 14. IF Reference Spurs (200 kHz) vs. VTUNE (1750 MHz, 200 kHz, 20 kHz)
0 -10 -20 0 -10 -20
TPC 17. RF Noise vs. VTUNE
PHASE NOISE - dBc/Hz
-30 -40 -50 -60 -70 -80 -90 -100 -40
PHASE NOISE - dBc/Hz
-20 0 20 40 60 80 100
-30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5
TEMPERATURE - C
TUNING VOLTAGE - V
TPC 15. RF Phase Noise vs. Temperature (1750 MHz, 200 kHz, 20 kHz)
TPC 18. IF Noise vs. VTUNE
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ADF4212L
0
FREQ/ MHz s11.REAL 0.97692 0.942115 0.961217 0.920667 0.897441 0.888164 0.850012 0.760189 0.767363 0.779511 0.761034 0.624825 0.635364 0.630242 0.634506 s11.IMAG -0.021077 -0.110459 -0.085802 -0.18583 -0.245482 -0.282399 -0.305457 -0.358884 -0.541032 -0.585687 -0.482539 -0.530108 -0.590526 -0.592498 -0.655932 FREQ/ MHz 1550 1650 1750 1850 1950 2050 2150 2250 2350 2450 2550 2650 2750 2850 2950 s11.REAL 0.561872 0.529742 0.514244 0.405754 0.379354 0.312959 0.322646 0.288881 0.199294 0.206914 0.168344 0.092764 0.036125 0.037007 -0.053842 s11.IMAG -0.648879 -0.668172 -0.702192 -0.714541 -0.703593 -0.802878 -0.80397 -0.807055 -0.758619 -0.725029 -0.770837 -0.778619 -0.706197 -0.716939 -0.736527
FIRST REFERENCE SPUR - dBc
-20
-40
-60
-80
-100
50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 1450
-120 -40
-20
0
20
40
60
80
100
TEMPERATURE - C
TPC 21. S Parameter Data for the RF Input
TPC 19. RF Spurs vs. Temperature
0
FIRST REFERENCE SPUR - dBc
-20
-40
-60
-80
-100
-120 -40
-20
0
20
40
60
80
100
TEMPERATURE - C
TPC 20. IF Spurs vs. Temperature
CIRCUIT DESCRIPTION Reference Input Section
RF/IF Input Stage
The Reference Input Stage is shown in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
The RF/IF Input Stage is shown in Figure 3. It is followed by a two-stage limiting amplifier to generate the CML (Current Mode Logic) clock levels needed for the prescaler.
BIAS GENERATOR 2k 1.6V AVDD 2k
RFINA
NC SW2 REFIN NC SW1 SW3 NO NC = NO CONNECT TO R COUNTER BUFFER 100k
RFINB
AGND
Figure 3. RF/IF Input Stage Figure 2. Reference Input Stage
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ADF4212L
Prescaler (P/P + 1) Phase Frequency Detector (PFD) and Charge Pump
The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio N, to be realized (N = PB + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF/IF input stage and divides it down to a manageable frequency for the CMOS A and B counters in the RF and IF sections. The prescaler in both sections is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. See Table IV and Table VI. It is based on a synchronous 4/5 core.
RF/IF A and B Counters
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a fixed delay element that sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.
HI D1 Q1 UP
U1
+IN CLR1
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less. Typically, they will work with 250 MHz output from the prescaler. Thus, with an RF input frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid.
Pulse Swallow Function
DELAY
U3
CHARGE PUMP
CP
HI -IN
CLR2 DOWN D2 Q2
The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows:
U2
Figure 5. RF/IF PFD Simplified Schematic
MUXOUT and Lock Detect
fVCO = ( P x B ) + A x f REFIN /R
fVCO = Output frequency of external voltage controlled oscillator (VCO) P B A = Preset modulus of dual modulus prescaler (8/9, 16/17, and so on) = Preset divide ratio of binary 13-bit counter (3 to 8191) = Preset divide ratio of binary 6-bit swallow counter (0 to 63)
[
]
The output multiplexer on the ADF4212L allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Table III and Table V. Figure 6 shows the MUXOUT section in block diagram form.
Lock Detect
fREFIN = External reference frequency oscillator R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383)
MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital Lock Detect is active high. It is set high when the phase error on three consecutive Phase Detector cycles is less than 15 ns. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain Analog Lock Detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected, it is high with narrow low going pulses.
DVDD
N = BP + A 12-BIT B COUNTER FROM RF INPUT STAGE LOAD PRESCALER P/P+1 LOAD 6-BIT A COUNTER
IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT MUX CONTROL RF R COUNTER OUTPUT RF N COUNTER OUTPUT RF ANALOG LOCK DETECT MUXOUT
TO PFD
MODULUS CONTROL
Figure 4. RF/IF A and B Counters
RF/IF R Counter
The 14-bit RF/IF R counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
Figure 6. MUXOUT Schematic
DGND
-10-
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ADF4212L
RF/IF Input Shift Register Table I. C2, C1 Truth Table
The ADF4212L digital section includes a 24-bit input shift register, a 14-bit IF R counter, and an 18-bit IF N counter (comprising a 6-bit IF A counter and a 12-bit IF B counter). Also present is a 14-bit RF R counter and an 18-bit RF N counter (comprising a 6-bit RF A counter and a 12-bit RF B counter). Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1, and DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed.
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch IF R Counter IF N Counter (A and B) RF R Counter RF N Counter (A and B)
Table II. Latch Summary
IF R COUNTER LATCH
LOCK DETECT PRECISION THREE-STATE CP IF PD POLARITY IF FO
IF CP CURRENT SETTING
15-BIT REFERENCE COUNTER
CONTROL BITS
DB23 IFCP2
DB22 IFCP1
DB21 IFCP0
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P1 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
IF N COUNTER LATCH
IF POWER-DOWN IF CP GAIN
IF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 P8
DB22 P7
DB21 P6
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P5 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
RF R COUNTER LATCH
THREE-STATE CP RF PD POLARITY RF LOCK DETECT RF FO
RF CP CURRENT SETTING
15-BIT RF REFERENCE COUNTER
CONTROL BITS
DB23
DB22
DB21
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P9 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
RFCP2 RFCP1 RFCP0
C2 (1) C1 (0)
RF N COUNTER LATCH
RF POWER-DOWN RF CP GAIN
RF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 P17
DB22 P16
DB21 P15
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P14 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
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ADF4212L
IF R COUNTER LATCH Table III. IF R Counter Latch Map
LOCK DETECT PRECISION THREE-STATE CP
IF PD POLARITY
IF FO
IF CP CURRENT SETTING
15-BIT IF REFERENCE COUNTER
CONTROL BITS
DB23 IFCP2
DB22 IFCP1
DB21 IFCP0
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P1 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
R15 0 0 0 0 . . . 1 1 P1 0 1 IF PD POLARITY NEGATIVE POSITIVE 1 1
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 32764 32765 32766 32767
P2 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 P11 FROM RF R LATCH 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
P4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
P3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH STATE RF REFERENCE DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT IF COUNTER RESET RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT RF COUNTER RESET IF AND RF COUNTER RESET
IFCP2 0 0 0 0 1 1 1 1
IFCP1 0 0 1 1 0 0 1 1
IFCP0 0 1 0 1 0 1 0 1
ICP (mA) 1.5k 1.1250 2.2500 3.3750 4.5000 5.6250 6.7500 7.7875 9.0000 2.7k 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411
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IF N COUNTER LATCH Table IV. IF N Counter Latch Map
IF POWER-DOWN
IF CP GAIN
IF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 P8
DB22 P7
DB21 P6
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P5 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
A6 P6 0 0 1 1 P7 0 1 P5 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 0 0 0 0 IF POWER-DOWN DISABLED ENABLED 0 . . . 1 1 1 1 P8 0 1 IF CP GAIN DISABLED ENABLED B12 0 0 . . . 1 1 1 1 B11 0 0 . . . 1 1 1 1 B10 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... B3 0 1 . . . 1 1 1 1 B2 1 0 . . . 0 0 1 1 B1 1 0 . . . 0 1 0 1
A5 0 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 0 1 0 0 . . . 0 0 1 1
A1 0 1 0 1 0 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 4 . . . 60 61 62 63
B COUNTER DIVIDE RATIO 3 4 . . . 4092 4093 4094 4095
N = BP+A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 - P)
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ADF4212L
RF R COUNTER LATCH Table V. RF R Counter Latch Map
THREE-STATE CP
RF PD POLARITY
RF LOCK DETECT
RF FO
RF CP CURRENT SETTING
15-BIT RF REFERENCE COUNTER
CONTROL BITS
DB23
DB22
DB21
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P9 R15 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
RFCP2 RFCP1 RFCP0
C2 (1) C1 (0)
R15 0 0 0 0 . . . 1 1 P9 0 1 RF PD POLARITY NEGATIVE POSITIVE 1 1
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 32764 32765 32766 32767
P10 0 1
RF CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
P11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
P4 P3 FROM IF R LATCH 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH STATE RF REFERENCE DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT IF COUNTER RESET RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT RF COUNTER RESET IF AND RF COUNTER RESET
RFCP2 0 0 0 0 1 1 1 1
RFCP1 0 0 1 1 0 0 1 1
RFCP0 1.5k 0 1 0 1 0 1 0 1 1.1250 2.2500 3.3750 4.5000 5.6250 6.7500 7.7875 9.0000
ICP (mA) 2.7k 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411
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ADF4212L
RF N COUNTER LATCH Table VI. RF N Counter Latch Map
RF POWER-DOWN
RF CP GAIN
RF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 P17
DB22 P16
DB21 P15
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P14 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (1) C1 (1)
A6 P15 P14 PRESCALER VALUE 0 0 1 1 0 1 0 1 8/9 16/17 32/33 64/65 0 0 0 0 P16 RF POWER-DOWN 0 1 DISABLED ENABLED 0 . . . 1 1 1 1 P17 RF CP GAIN 0 1 DISABLED ENABLED B12 0 0 . . . 1 1 1 1 B11 0 0 . . . 1 1 1 1 B10 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... B3 0 1 . . . 1 1 1 1 B2 1 0 . . . 0 0 1 1 B1 1 0 . . . 0 1 0 1
A5 0 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 0 1 0 0 . . . 0 0 1 1
A1 0 1 0 1 0 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 4 . . . 60 61 62 63
B COUNTER DIVIDE RATIO 3 4 . . . 4092 4093 4094 4095
N = BP+A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 - P)
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ADF4212L
PROGRAM MODES
Table III and Table V show how to set up the Program Modes in the ADF4212L. The following should be noted: 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either IF or RF Analog Lock Detect is selected, then the MUXOUT pin will show a logic high with narrow low going pulses. When the IF/RF Analog Lock Detect is chosen, then the locked condition is indicated only when both IF and RF loops are locked. 2. The IF Counter Reset Mode resets the R and AB counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset Mode resets the R and AB counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset Mode does both of the above. Upon removal of the reset bits, the AB counter resumes counting in close alignment with the R counter. (Maximum error is one prescaler output cycle.) 3. The Fastlock Mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to "1."
IF Power-Down
The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. The input register and latches remain active and are capable of loading and latching data during all power-down modes. The IF/RF section of the devices will return to normal powered-up operation immediately upon LE latching a "0" to the appropriate Power-Down Bit.
IF SECTION PROGRAMMABLE IF REFERENCE (R) COUNTER
If control bits C2, C1 are 0, 0, the data is transferred from the input shift register to the 14-bit IFR counter. Table III shows the input shift register data format for the IFR counter and the divide ratios possible.
IF Phase Detector Polarity
P1 sets the IF Phase Detector Polarity. When the IF VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table III.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table III.
IF PROGRAM MODES
It is possible to program the ADF4210 family for either synchronous or asynchronous power-down on either the IF or RF side.
Synchronous IF Power-Down
Table III and Table V show how to set up the Program Modes in the ADF4212L.
IF Charge Pump Currents
Programming a "1" to P7 of the ADF4212L will initiate a powerdown. If P2 of the ADF4212L has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and complete the power-down.
Asynchronous IF Power-Down
IFCP2, IFCP1, IFCP0 program Current Setting for the IF charge pump. See Table III.
PROGRAMMABLE IF AB COUNTER
If P2 of the ADF4212L has been set to "1" (three-state the IF charge pump) and P7 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the IF PowerDown Bit (P7).
Synchronous RF Power-Down
If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. The N counter consists of a 6-bit swallow counter (A counter) and 12-bit programmable counter (B counter). Table IV shows the input register data format for programming the IF AB counter and the divide ratios possible.
IF Prescaler Value
Programming a "1" to P16 of the ADF4212L will initiate a power-down. If P10 of the ADF4212L has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down.
Asynchronous RF Power-Down
P5 and P6 in the IF A, B Counter Latch set the IF prescaler values. See Table IV.
IF Power-Down
Table III and Table V show the power-down bits in the ADF4212L.
IF Fastlock
If P10 of the ADF4212L has been set to "1" (three-state the RF charge pump) and P16 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the RF PowerDown Bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop's R and AB dividers to their load state conditions and the IF/RF input section is debiased to a high impedance state.
The IF CP Gain Bit (P8) of the IF N Register in the ADF4212L is the Fastlock Enable Bit. Only when this is "1" is IF Fastlock enabled. When Fastlock is enabled, the IF CP current is set to maximum value. Also an extra loop filter damping resistor to ground is switched in using the FL O pin, thus compensating for the change in loop characteristics while in Fastlock. Since the IF CP Gain Bit is contained in the IF N Counter, only one write is needed to both program a new output frequency and initiate Fastlock. To come out of fastlock, the IF CP Gain bit on the IF N Register must be set to "0." See Table IV.
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ADF4212L
RF SECTION Programmable RF Reference (R) Counter RF Power-Down
If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RFR counter. Table V shows the input shift register data format for the RFR counter and the divide ratios possible.
RF Phase Detector Polarity
Table III and Table V show the power-down bits in the ADF4210 family.
RF Fastlock
P9 sets the IF Phase Detector Polarity. When the RF VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table V.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table V.
RF Program Modes
The RF CP Gain Bit (P17) of the RF N Register in the ADF4212L is the Fastlock Enable Bit. Only when this is "1" is IF Fastlock enabled. When Fastlock is enabled, the RF CP current is set to maximum value. Also, an extra loop filter damping resistor to ground is switched in using the FL O pin, thus compensating for the change in loop characteristics while in Fastlock. Since the RF CP Gain Bit is contained in the RF N counter, only one write is needed to both program a new output frequency and initiate Fastlock. To come out of Fastlock, the RF CP Gain Bit on the RF N Register must be set to "0." See Table VI.
APPLICATION SECTION Local Oscillator for GSM Handset Receiver
Table III and Table V show how to set up the Program Modes in the ADF4212L.
RF Charge Pump Currents
RFCP2, RFCP1, RFCP0 program Current Setting for the RF charge pump. See Table V.
Programmable RF N Counter
If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF N (A + B) counter. The N counter consists of a 6-bit swallow counter (A counter) and 12-bit programmable counter (B counter). Table IV shows the input register data format for programming the RF N counter and the divide ratios possible. See Table VI.
RF Prescaler Value
Figure 7 shows the ADF4212L being used with a VCO to produce the required LOs for a GSM base station transmitter or receiver. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 . Typical GSM systems would have a 13 MHz TCXO driving the Reference Input without any 50 termination. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference. The RF output frequency range is 880 MHz to 915 MHz. The loop filter is designed to give a 20 kHz loop bandwidth. The filter is set up for a 5 mA charge pump current, and the VCO sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz. The filter is again designed to have a bandwidth of 20 kHz, and the system is programmed to give channel steps of 200 kHz.
P14 and P15 in the RF A, B Counter Latch set the RF prescaler values. See Table VI.
IFOUT VP 100pF 18 18 100pF 3.3k 1.3nF 620pF VP2 CPIF 2.7k 13nF RSET 2.7k MUXOUT 100pF IFIN
DGNDRF AGNDRF DGNDIF AGNDIF
RFOUT VDD VP 100pF VDD2 VDD1 VP1 CPRF 100pF 18 18
VCC VCO190-540T
VCC VCO190-902U
18
18
ADF4212L
LOCK DETECT
100pF
RFIN CLK DATA LE 51 SPI COMPATIBLE SERIAL BUS
51 FREFIN
1000pF 1000pF REFIN 51
DECOUPLING CAPACITORS (22 F/10pF) ON V DD, VP OF THE ADF4212L AND ON V CC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4212L
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ADF4212L
Wideband PLL
Many of the wireless applications for synthesizers and VCOs in PLLs are narrow-band in nature. These applications include the various wireless standards like GSM, DSC1800, CDMA, or WCDMA. In each of these cases, the total tuning range for the local oscillator is less than 100 MHz. However, there are also wideband applications where the local oscillator could have up to an octave tuning range. For example, cable television tuners have a total range of about 400 MHz. Figure 8 shows an application where the ADF4212L is used to control and program the Micronetics M3500-1324. The loop filter was designed for an RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP multiplied by the gain factor of 4), VCO KD of 80 MHz/V (sensitivity of the M3500-1324 at an output of 2100 MHz) and a phase margin of 45 degrees.
In narrow-band applications, there is generally a small variation in output frequency (generally less than 10%) and also a small variation in VCO sensitivity over the range (typically <10%). However in wideband applications both of these parameters have a much greater variation. Variations in these parameters will change the loop bandwidth. This in turn can affect stability and lock time. By changing the programmable ICP, it is possible to get compensation for these varying loop conditions and ensure that the loop is always operating close to optimal conditions.
VDD
VP
20V 3k AD820
12V VCC V_TUNE OUT
RFOUT
1k VDD1 VDD2 1000pF FREFIN 51 1000pF REFIN VP1 VP2 CPRF RSET 3.9nF 2.7k 20k 27nF 470 130pF
100pF 100pF 18 18 18
M3500-1324 GND
ADF4212L
SPI COMPATIBLE SERIAL BUS CLK DATA LE
DGNDRF AGNDRF DGNDIF
MUXOUT
LOCK DETECT 100pF
AGNDIF
RFIN 51
DECOUPLING CAPACITORS ON V DD, VP OF THE ADF4212L, ON V CC OF THE AD820 AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO SIMPLIFY THE SCHEMATIC.
Figure 8. Wideband PLL Circuit
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ADF4212L
Interfacing ADSP-2181 Interface
The ADF4212L has a simple SPI compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will get transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 s. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 9 shows the interface between the ADF4212L and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4212L needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF4212L, four writes (one each to the R counter latch and the AB counter latch for both IF and RF side) are required for the output to become active. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 180 kHz.
Figure 10 shows the interface between the ADF4212L and the ADSP-21xx Digital Signal Processor. As previously discussed, the ADF4212L needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the Autobuffered Mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
ADuC812
SCLK MOSI
ADF4212L
SCLK SDATA LE
I/O PORTS
CE MUXOUT (LOCK DETECT)
Figure 9. ADuC812 to ADF4212L Interface
ADSP-21xx
SCLK DT TFS I/O FLAGS
ADF4212L
SCLK SDATA LE CE MUXOUT (LOCK DETECT)
Figure 10. ADSP-21xx to ADF4212L Interface
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ADF4212L
OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package (TSSOP) (RU-20)
Dimensions shown in millimeters
20
11
4.50 4.40 4.30
1 10
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 COPLANARITY 0.19 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AC
20-Lead Frame Chip Scale Package (LFCSP) 4x4 mm Body (CP-20)
Dimensions shown in millimeters
4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR
TOP VIEW
0.60 MAX
16 15
20 1
3.75 BSC SQ 0.75 0.55 0.35
11 10
BOTTOM VIEW
6 5
2.25 2.10 SQ 1.95
12 MAX 1.00 0.90 0.80 SEATING PLANE 0.50 BSC
0.70 MAX 0.65 NOM 0.05 0.02 0.00
0.30 0.23 0.18 COPLANARITY 0.08
0.25 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS
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PRINTED IN U.S.A.
C02774-0-11/02(0)
6.60 6.50 6.40

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